In semiconductor technology and in microelectronics, the dimensions of structures are becoming smaller and smaller. In memory production today, e.g., structures with a width of less than 400 nm are produced using optical lithography in combination with the masking technique. Photholithographic processes are vital steps in the fabrication of, e.g., semiconductor devices. In a photolithographic process, an exposure light, usually ultraviolet (UV) light is used to expose a photoresist-coated semiconductor wafer through a mask (in the following called photomask). The purpose of the photolithographic process is to transfer a set of patterns representative of the circuit layer onto the wafer. The patterns on the photomask define the positions, shapes and sizes of various circuit elements such as diffusion areas, metal contacts and metallization layers, on the wafer.
In optical lithography a limit can be expected at approximately 150 nm because of diffraction effects.
However, structures with even smaller dimensions are required for new applications such as single-electron transistors or molecular electronic components. In the case of very high-frequency circuits this is also true in conventional electronics. There is also a need to reduce, e.g., the read and write dimensions in thin film magnetic heads. In addition to that, micro structures having a very high aspect ratio of about 5 to 30 and greater will be needed.
Today's photolithographical techniques are still restricted by the wavelength of the used exposure light to arrive at critical dimensions as small as possible. Reduction of the critical dimensions was done in most cases by the reduction of the wavelength of radiation, i.e., starting with UV exposure and proceeding to DUV exposure, electron radiation and X-rays. X-ray lithography, e.g., makes it possible to image dimensions of less than 100 nm. In electron and ion beam lithography, structures as small as 10 nm can be generated with high-energy particles. However, this requires expensive vacuum systems and beam guidance systems. In addition, problems can occur with sensitive components due to radiation damage in the substrate, because the high-energy particles can penetrate through the resist layers required for etching processes.
U.S. Pat. No. 5,837,426 discloses a photolithographic process which provides reduced line widths or reduced inter-element line spaces for the circuit elements on an IC chip, allowing the IC chip to have a higher degree of integration. This photholithographic process includes a double-exposure process on the same wafer defined by placing either the same photomask at two different positions or by using two photomasks.
In U.S. Pat. No. 6,042,993 a photholithographic structure generation process for structures in the sub-200 nm range is disclosed wherein a layer of amorphous hydrogen-containing carbon with an optical energy gap of <1 eV or a layer of sputtered amorphous carbon is applied as the bottom resist to a substrate; the bottom layer resist is provided with a layer of an electron beam-sensitive silicon-containing or silylatable photoresist as the top resist; the top resist is then structured by means of scanning tunneling microscopy (STM) or scanning force microscopy (SFM) with electrons of an energy of <80 eV; and the structure is subsequently transferred to the bottom resist by etching with an anisotropic oxygen plasma and is next transferred to the substrate by plasma etching.
However, there is still a need to produce coating thicknesses from some nm into the μm range.